
Lead Designer for Advanced Low Power Solutions
1 day ago
We are seeking a highly skilled Sr Physical Design Engineer with expertise in top-level floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, and timing analysis/closure.
- The ideal candidate will have experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias.
This position requires strong technical guidance, mentoring of Physical Design Engineers, and interface with front-end ASIC teams to resolve issues.
- Responsibilities include Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques and Timing closure on DDR2/DDR3/PCIE interfaces.
- A background in ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure is essential.
- Experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools is also required.
- This role requires expertise in scripting languages such as PERL, TCL.
- Strong Physical Verification skill set is necessary.
- Static Timing Analysis in Primetime or Primetime-SI is also required.
Requirements:
5-15 years of experience
Qualifications:
-
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