Lead ASIC Physicist
6 days ago
We are seeking an experienced Senior Physical Design Engineer to lead the implementation of complex chips on advanced process nodes. This role involves designing, developing, and implementing physical design flows for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
- Responsibilities:
- Lead the physical design team to implement full-chip designs on 16nm and 7nm processes.
- Develop and maintain a thorough understanding of EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
- Collaborate with the methodology team to improve the physical design flow and solve implementation challenges.
- Design automation, timing constraints, SI prevention, power reduction, and experience with Synopsys/Cadence/Mentor place and route tools.
Requirements:
- Minimum 4+ years of experience in ASIC physical design.
- Strong communication skills and hands-on TCL/Perl development skills.
- Proven track record of taping out complex chips on advanced process nodes.
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