
Synthesizing Complex Digital Systems
3 days ago
Eteros Technologies is seeking an experienced Lead to drive the synthesis, static timing, and DFT efforts for advanced mixed signal chips. This highly visible role will be at the heart of Soc design effort, interfacing with all disciplines to deliver functional products to customers quickly.
The ideal candidate must have thorough knowledge of ASIC design timing closure flow and methodology. A BTech/MTech/PhD degree with 6+ years of experience in ASIC timing constraints generation and timing closure is required. Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing is essential. Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm, is required.
Key Responsibilities:
- Full chip and block level timing closure ownership throughout the entire project cycle.
- Developing and maintaining methodology and flows related to timing verification and closure.
- Generating block and full chip timing constraints.
- Analyzing timing reports.
- Utilizing scripting techniques to develop insights and drive rapid timing closure.
Requirements:
- Thorough knowledge of ASIC design timing closure flow and methodology.
- Expertise in STA tools (Tempus and Primetime).
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes.
- Strong communication skills.
- Proficiency in scripting languages (Tcl and Perl).
- Ability to solve complex problems and independently drive tasks to completion in a timely manner.
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