
Static Timing Engineer
5 days ago
We are looking for skilled STA engineers to join our team. As a STA engineer, you will play a crucial role in ensuring the timely and efficient completion of projects.
The ideal candidate should have a minimum of 5+ years of experience in STA engineering. They should possess excellent knowledge of timing closure, congestion, and area-sensitive designs. Additionally, they should be well-versed in industry-standard tools from Synops or Cadence.
The selected candidate will work closely with the FE team to develop and clean up constraints. They will also collaborate with partition/block owners to provide timing ECOs for timing closure. Furthermore, they should have expertise in advanced timing closure techniques and methodologies.
Beyond technical skills, we value candidates with strong scripting and communication skills. A preference will be given to candidates with experience working on DSM technologies, particularly TSMC 5nm and below.
If you are a motivated and detail-oriented professional with a passion for STA engineering, we encourage you to apply.
Key Responsibilities:
- Develop and maintain timing closure plans for high-frequency designs
- Collaborate with the FE team to develop and clean up constraints
- Work with partition/block owners to provide timing ECOs for timing closure
- Apply advanced timing closure techniques and methodologies
- Provide expertise in industry-standard tools from Synops or Cadence
Requirements:
- Minimum 5+ years of experience in STA engineering
- Excellent knowledge of timing closure, congestion, and area-sensitive designs
- Strong scripting and communication skills
- Prior experience working on DSM technologies (TSMC 5nm and below preferred)
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