Static Timing Analysis Engineer

6 days ago

Bengaluru, Karnataka, India beBeeTiming Full time ₹ 2,02,55,680 - ₹ 2,51,90,200
Job Title: Timing Optimization Specialist

This is a critical role that requires deep expertise in Static Timing Analysis (STA) tools like Synopsys PrimeTime and Cadence Tempus. You will be responsible for owning full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages.

The ideal candidate will have a strong background in STA, timing constraints development, and scripting languages. They should be able to work closely with cross-functional teams to ensure timely project delivery.

  • Responsibilities:
  • Owning full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages.
  • Developing and validating timing constraints (SDC) for blocks, partitions, and full-chip designs.
  • Performing timing analysis using industry-standard tools like PrimeTime and Tempus.
  • Collaborating with design and architecture teams to define timing requirements and resolve timing violations.
  • Analyzing timing scenarios, margins, and corner cases.
  • Integrating third-party IPs and deriving timing signoff requirements.
  • Optimizing timing paths and reducing signoff corners by merging modes.
  • Automating STA flows using scripting languages like TCL, Perl, and Python.
  • Required Skills and Qualifications:
  • Deep expertise in Static Timing Analysis (STA) tools like Synopsys PrimeTime and Cadence Tempus.
  • Proficient in writing and validating SDC constraints.
  • Strong skills in scripting languages like TCL, Perl, and Python for automation.
  • Understanding of synthesis, physical design, and backend flows.
  • Experience with timing corners, process variations, and signal integrity.
  • Familiarity with tools like Synopsys GCA (Galaxy Constraint Analyzer).
  • Preferred Skills:
  • Tool proficiency in Genus, Timevision, Fishtail, and Tweaker.
  • Knowledge of Low-Power Design and UPF.
  • Handling custom IP integration, PLLs, SerDes, ADC/DAC, GPIO, and HSIO.
  • Strong interpersonal skills for cross-functional teamwork.
  • Ability to guide and mentor junior engineers.
  • Familiarity with advanced nodes like 3nm, 5nm, 7nm, and FinFET.
  • Additional Information:
  • The ideal candidate will have a strong background in STA, timing constraints development, and scripting languages.
  • They should be able to work closely with cross-functional teams to ensure timely project delivery.
  • Excellent communication and problem-solving skills are essential for this role.

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