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DFT Architects

2 weeks ago

Bengaluru, Karnataka, India beBeeDesign Full time ₹ 1,20,00,000 - ₹ 2,00,00,000

We are seeking an experienced Design for Test Engineer to lead our ATPG efforts.

 

Key Responsibilities
  • Implementation and verification of DFT architecture and features
  • Scan insertion and ATPG pattern generation
  • ATPG patterns verification with gate-level simulation
  • Test coverage and test cost reduction analysis
  • Post silicon support to ensure successful bring up and enhance yield learning

 

Requirements
  • Understanding of Design for Test methodologies and DFT verification experience (e.g., IEEE 1500, JTAG 1149.x, Scan, memory BIST etc.)
  • Experience with Mentor TestKompress and/or Synopsys Tetramax/DFTMAX
  • Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

 

Preferred Qualifications include a Bachelor's or Master's degree in Computer Engineering/Electrical Engineering.