
DFT Architect
1 day ago
Job Overview
We are seeking an experienced Design for Test Engineer to join our team. This role will involve developing and debugging scripting solutions using Python, Perl, and TCL for automation of Design for Test flows.
Main Responsibilities:
- Develop DFT architectures and methodologies including Scan Insertion & Verification, ATPG, MBIST, JTAG / Boundary Scan
- Evaluate, deploy, and optimize DFT tool flows with EDA vendors
- Automate repetitive tasks using scripting to improve efficiency and reduce errors
- Support test vector generation and validation for Automated Test Equipment (ATE)
- Provide technical guidance and mentorship to junior engineers in the DFT team
Requirements:
- Strong expertise in DFT architectures and methodologies including but not limited to: Scan Insertion & Verification, ATPG, MBIST, JTAG / Boundary Scan
- Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA)
- Proven ability to develop and debug high-quality DFT solutions within tight schedules
- Solid understanding of System on Chip (SoC) design cycle, RTL to GDSII flow, and test requirements
PREFERRED SKILLS:
- Knowledge of low-power DFT techniques (power-aware ATPG, retention flops, etc.)
- Experience with post-silicon bring-up and ATE patterns
- Familiarity with safety-critical standards (ISO 26262, DO-254, etc.)
- Exposure to High-Speed IO testing (SERDES, DDR, etc.)
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