
DFT Architect
6 days ago
We are seeking a skilled professional to fill the position of Design-for-Test (DFT) Engineer. The ideal candidate will have 3–5 years of experience in ASIC design and verification with a strong focus on DFT methodologies.
Key Responsibilities:
- Develop and implement DFT architectures, including scan insertion, ATPG, MBIST, and boundary scan.
- Work on RTL design modifications for DFT features.
- Generate and validate test vectors using tools like Tetramax/Fastscan.
- Run gate-level simulations and debug test coverage issues.
- Perform pattern validation on emulation/silicon platforms.
- Collaborate with RTL, PD, and validation teams for seamless DFT integration.
Required Skills and Qualifications:
- Strong knowledge of DFT concepts: scan, compression, boundary scan, ATPG, BIST (LBIST/MBIST).
- Experience with tools such as Synopsys DFT Compiler, Tetramax, Mentor Tessent.
- Scripting skills in Python, Perl, or TCL for automation.
- Familiarity with STA, synthesis, and timing constraints.
- Good understanding of RTL-to-GDS flow.
Benefits of This Opportunity:
- Exposure to automotive or high-reliability designs.
- Experience with silicon bring-up and pattern debug.
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