Senior DFT Verification Specialist

2 days ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Title: Senior DFT Verification Engineer

 

Role Overview:

The ideal candidate will be responsible for verifying DDR IP/subsystems using pattern-based testing methodologies. This involves generating and validating JTAG-based test patterns specifically for DDR interfaces using industry-standard tools and flows.

Key Responsibilities:

  • Verify DDR IP/subsystems using pattern-based testing methodologies.
  • Generate and validate JTAG-based test patterns specifically for DDR interfaces using industry-standard tools and flows.
  • Perform Gate-Level Simulations (GLS) to validate generated test patterns and ensure correct functionality in the post-synthesis/post-layout netlists.
  • Develop verification plans, write testbenches, and debug test pattern failures across RTL and gate-level simulations.
  • Interface with RTL, validation, and test teams to ensure seamless test integration and silicon readiness.
  • Contribute to ATPG/MBIST pattern integration and test coverage improvements for DDR-related logic.
  • Ensure patterns meet structural and functional test goals without impacting design performance.
  • Review timing reports and ensure pattern compliance with design timing requirements.
  • Closely collaborate with DFT architects to enhance test insertion methodologies for high-speed interfaces like DDR.
Required Skills and Qualifications:

To be successful in this role, you will need the following skills and qualifications:

  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 4-9 years of industry experience in DFT Verification, with specific focus on DDR IP or DDR subsystem-level testing.
  • Strong knowledge of DFT concepts including JTAG, boundary scan, scan insertion, ATPG, and MBIST.
  • Proven experience in pattern generation and gate-level simulation for high-speed interfaces (DDR3/DDR4/LPDDR4/DDR5).
  • Solid understanding of digital logic design, SoC architecture, and memory controller interfaces.
  • Hands-on experience with Verilog/VHDL, SystemVerilog for testbenches, and simulation tools like VCS, NC-Sim, or Questa.
  • Familiarity with DFT tools like TetraMAX, TestMAX, Tessent, or equivalent.
  • Experience in post-synthesis/post-layout simulations, including STA timing reviews and glitch analysis.
  • Proficient in scripting languages: Tcl, Perl, Python, or Shell.
  • Strong debugging skills and ability to root-cause test failures across RTL and GLS domains.
Preferred Qualifications:

The following qualifications are preferred but not required:

  • Experience with low-power testing and UPF-based flows.
  • Knowledge of SoC-level DFT integration, including hierarchical scan and clock domain crossings.
  • Familiarity with lab environments and post-silicon validation.
  • Understanding of DDR protocol standards and compliance requirements.

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