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Dft Verification Engineer
2 weeks ago
Dear DFT Experts, are you ready to take your career to the next level with cutting-edge DDR validation projects?
Job Title: DFT Verification Engineer DDR & GLS Focus
Location: Bangalore
Notice Period: Immediate to 30 Days
Job Overview:
We're hiring experienced DFT Verification Engineers (4–14 years) who are passionate about DDR IP/subsystem testing and skilled in Gate-Level Simulations (GLS). If you thrive in high-performance environments and have hands-on knowledge of silicon pattern generation through JTAG, this is your opportunity to make an impact in a global semiconductor leader's project.
Key Responsibilities:
- Develop and execute DFT verification flows for DDR IP/Subsystems
- Generate silicon test patterns for DDR interfaces via JTAG
- Perform and debug Gate-Level Simulations (GLS) using timing-accurate models
- Collaborate closely with DFT, STA, and RTL design teams
- Ensure functional, timing, and power intent validation of DDR test patterns
What We're Looking For:
- Strong real-time experience in DDR verification
- Deep understanding of JTAG test pattern generation
- Proficiency in GLS execution and debug
- Solid grasp of digital design, timing, and DFT concepts
- Strong scripting and automation mindset (Python/Perl/TCL preferred)
Why Join Us?
- Work on high-impact DFT projects in the DDR domain
- Collaborate with top-tier design and verification teams
- Be part of an innovation-driven and growth-oriented environment
Career growth + Recognition for technical excellence
Interested? Let's connect
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