DFT Engineer

1 day ago

Bengaluru, Karnataka, India CODERS BRAIN TECHNOLOGY PRIVATE LIMITED Full time ₹ 3,59,000 - ₹ 15,50,129 per year

About the Role

We are looking for an experienced Design-for-Test (DFT) Engineer with strong expertise in scan insertion, MBIST, JTAG, and ATPG methodologies. The ideal candidate should have hands-on experience in DFT architecture, pattern generation, validation, and debug across block and full-chip levels, along with a solid understanding of RTL and synthesis flows.

Key Responsibilities

  • Perform scan insertion, MBIST, JTAG, and ATPG pattern generation at block and full-chip levels.
  • Execute pattern validation with/without timing, including DFT mode timing analysis and sign-off.
  • Work on DFT architecture design: boundary scan (JTAG), scan compression, scan chain insertion, and test point insertion.
  • Generate scan patterns and coverage statistics for stuck-at, transition faults, bridging, and cell-aware models.
  • Conduct ATPG coverage analysis and provide optimization recommendations.
  • Utilize Synopsys tools (DFT MAX, TetraMAX, VCS) for DFT implementation and debug.
  • Collaborate with RTL integration, synthesis, constraints, and timing teams to resolve cross-functional issues.
  • Perform gate-level simulations and debug for pattern verification.
  • Ensure DFT checks and compliance using Spyglass DFT.
  • (Optional) Support post-silicon debug activities as needed.

Required Skills & Qualifications

  • 5+ years of hands-on experience in DFT design and verification.
  • Strong knowledge of DFT concepts, ATPG, and pattern validation.
  • Expertise in Synopsys DFT tools (DFT MAX, TetraMAX, VCS).
  • Experience with Verilog, RTL simulation, and gate-level verification.
  • Familiarity with Spyglass DFT and static DFT rule checks.
  • Strong debugging and problem-solving skills across design and test domains.
  • Excellent communication and cross-functional collaboration skills.

Job Type: Full-time

Pay: ₹359, ₹1,550,129.97 per year

Work Location: In person

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