Senior DFT Specialist

6 days ago

Erode, Tamil Nadu, India beBeeDft Full time ₹ 1,80,00,000 - ₹ 2,50,00,000
About the Role

We are seeking a seasoned Digital Fault Tolerance (DFT) Engineer to lead our DFT strategy and architecture for complex ASIC/SoC projects.

Key Responsibilities:
  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects, ensuring seamless integration with cross-functional teams.
  • Implement and verify DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
  • Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up, owning DFT signoff, timing closure, and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor junior DFT engineers, conduct design reviews, and training sessions.
  • Develop and maintain DFT automation scripts and infrastructure.
Requirements:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • At least 7 years of experience in DFT for complex ASIC or SoC designs, with expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows, proficient in scripting languages for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.
What We Offer
  • Opportunities for professional growth and development.
  • A dynamic and collaborative work environment.

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