Senior ASIC Design Verification Engineer

3 days ago

Erode, Tamil Nadu, India beBeeDftEngineer Full time ₹ 1,80,00,000 - ₹ 2,00,00,000
Lead DFT Architect

Drive the development of complex SoC/ASIC designs, focusing on DFT architecture and planning.

This role requires strong technical leadership skills to mentor junior engineers, collaborate with cross-functional teams, and ensure high-quality testability and manufacturability of silicon products.

Key Responsibilities:
  • Define and implement DFT strategy and architecture for multiple ASIC/SoC projects.
  • Implement and verify DFT features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), and IJTAG (1687).
  • Manage the end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
  • Develop and maintain DFT automation scripts and infrastructure.
Required Skills and Experience:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence/others.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.
Preferred Qualifications:
  • Experience with hierarchical DFT and low-power DFT methodologies (UPF).
  • Exposure to post-silicon validation and failure analysis.
  • Familiarity with safety-critical designs (ISO 26262) and functional safety.
  • Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).

Join a dynamic team of top-tier engineers and global semiconductor leaders, enjoying competitive salary, leadership exposure, and fast-track growth opportunities.

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