
Chief Verification Specialist
2 days ago
Job Title: Senior Design Verification Engineer
">Role Summary:
">As a senior design verification engineer, you will be responsible for leading the development and implementation of verification environments for complex digital and analog designs. This role requires a strong technical background in verification methodologies, as well as excellent communication and leadership skills.
">Key Responsibilities:
">- Develop and maintain verification environments for digital and analog designs.
- Collaborate with cross-functional teams to define verification requirements and develop testbenches.
- Implement and execute verification plans, including simulation and emulation.
- Debug and resolve issues found during verification, working closely with designers and other engineers.
- Develop and maintain code coverage metrics and functional coverage reports.
- Perform UPF (Unified Power Format) based power-aware simulations.
- Code and implement assertion and functional coverage bins in SVA (System Verilog Assertions).
- Prepare and conduct reviews of verification sign-off documents to ensure SOC tape-out quality.
Requirements:
">To succeed in this role, you will need:
">- 7+ years of experience in verification engineering.
- Strong understanding of SystemVerilog, UVM (Universal Verification Methodology), and C programming languages.
- Experience with simulation tools such as Synopsys and Cadence.
- Excellent communication and leadership skills.
- Ability to work in a fast-paced environment and prioritize multiple tasks.
Benefits:
">This role offers:
">- Opportunities for professional growth and development.
- A dynamic and collaborative work environment.
- Competitive salary and benefits package.
Other Information:
">This is a full-time position. We are an equal opportunities employer.
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