Senior ASIC Design Engineer

3 days ago

Erode, Tamil Nadu, India beBeeEngineering Full time ₹ 20,00,000 - ₹ 25,00,000

As a Senior ASIC STA Engineer, you will lead synthesis, static timing and DFT efforts for an advanced mixed signal chip.

This highly visible role is part of a highly talented team at the heart of the Soc design effort, interfacing with all disciplines to get functional products to customers quickly.

You will be responsible for full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).

Key responsibilities include developing and maintaining methodology and flows related to timing verification and closure, generating block and full chip timing constraints, analyzing timing reports, and utilizing scripting techniques to develop insights and drive rapid timing closure.

The position requires thorough knowledge of the ASIC design timing closure flow and methodology, expertise in STA tools (Tempus and Primetime), and familiarity with low-power techniques including clock gating, power gating and millivoltage designs.

Strong communication skills and ability to solve complex problems independently are essential. You should also be able to work under limited supervision and take complete accountability.

Opportunities for career development and growth, competitive compensation, medical benefits, and more make this a unique opportunity to showcase your ability and experience world-wide from day one while learning from some of the world's most well-respected companies.

Eteros engineers are treated as an integral part of the customer team and routinely take end-to-end ownership and delivery of projects.

As an Eteros engineer, you will continuously learn, grow and prepare yourself for fast-track career development and longevity.

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