AI Hardware Design Lead
2 days ago
The Lead Architect of High-Performance AI Blocks will be responsible for designing and implementing high-performance TPUs/MPUs and other related AI blocks using RTL. The role requires a strong grasp of digital design fundamentals, computer architecture, virtual memory, and high-speed data-path design.
The ideal candidate should have a clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts and proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis is also required.
The key responsibilities of this role include:
- Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL.
- Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure.
- Optimize design for power, performance, and area (PPA).
- Interface with physical design and DFT engineers for seamless integration.
- Drive design reviews, write design documentation, and support post silicon bring-up/debug.
As a valued member of our team, you will collaborate with cross-functional teams to define and implement next-generation AI architectures.
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