DFT Architecture Lead

6 days ago


Malappuram, Kerala, India beBeeDigitalFaultTolerance Full time ₹ 20,00,000 - ₹ 30,00,000

Seeking a seasoned Digital Fault Tolerance (DFT) Engineer to spearhead the development and implementation of cutting-edge DFT architectures for ASIC/SoC designs.

This role requires collaboration with RTL and physical design teams to ensure seamless integration of DFT features. Key responsibilities include:

  1. ">
  2. Developing and implementing DFT architectures for ASIC/SoC designs.
  3. Inserting and verifying scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures.
  4. Collaborating with RTL and physical design teams to ensure seamless integration of DFT features.
  5. Generating and validating test patterns using ATPG tools for stuck-at, transition, and path delay faults.
  6. Performing fault simulation and coverage analysis to optimize test quality.
  7. Supporting silicon bring-up and debug of test-related issues.
  8. Working with ATE teams to develop test programs and support production testing.

The ideal candidate will have 3 years of experience in DFT engineering, excellent communication skills, and a passion for innovation. If you are interested in this exciting opportunity, please submit your updated resume to janagaradha.n@acldigital.com



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