Verification Engineer
4 weeks ago
We are seeking a skilled Design Verification Engineer to join our Traffic Management Team at Broadcom Inc.
Key Responsibilities:
- Plan, verify, and close coverage for RTL dealing with Traffic/Buffer Management in Ethernet Switch/Routers based on UVM methodology.
- Identify and create functional coverage and follow the coverage-driven methodology.
- Collaborate with design and verification teams to close assigned tasks.
- Understand design specifications, define verification scope, develop test plans, tests, and verification infrastructure, and verify design correctness.
- Work with emulation, post-silicon, and SW teams as needed.
Requirements:
- B.E./B.Tech with 12+ years or M.E./M.Tech with 10+ years of relevant experience.
- Expertise in block, sub-system, and top-level verification & simulation optimizations.
- Knowledge of DV methodologies like UVM/VMM and exposure to industry-standard verification tools for simulation and debug.
- Experience with scripting languages like Perl/Python/Shell.
- Gate-level simulation experience with SDF annotation.
- Self-motivated individual with a strong background in planning, developing, and working in functional coverage-based constrained random verification environments.
Preferred Qualifications:
- Networking fundamentals - switch/router basics.
- Buffer management concepts - scheduling concepts, congestion, linked list, different memory organizations.
- Strong interpersonal and communication skills.
- Experience in verifying complex verification environments with complex, cycle-accurate checkers.
Broadcom Inc. is an equal opportunity employer.
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