Senior Verification Engineer

2 weeks ago


Bengaluru, Karnataka, India Molex Full time

Job Summary

The Senior Verification Engineer will lead the development of verification architecture, implement verification environment for block level, SoC subsystems, and SOC top level design using advanced verification methodologies. He/She will define overall verification strategies, methodologies, and simulation environment, and work with RTL designers, system architects, and block level verification engineers to develop top level verification requirements and test plans based on specifications.

Key Responsibilities

· Develop, maintain, and publish verification specifications.

· Analyze and debug simulation failures.

· Generate code coverage and functional coverage report.

· Run gate level simulation and debug them.

· Perform constraint assertion-based verification.

Requirements

· BS in EE with 3+ years of experience or MS in EE with 1+ year experience.

· Strong knowledge with ASIC Simulation Tool and Verification Language: all sign-off simulators, Verdi/Siloti.

· Fluent in verification language such as UVM/OVM/System Verilog, Vera, Verilog.

· Experience in writing Test-plans and creating directed and random test cases.

· Strong scripting skills in Perl, Python, Linux shells, etc.



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