Senior Verification Engineer
1 month ago
L&T Technology Services is seeking a highly skilled Senior DV Engineer to lead our design verification efforts.
Key Responsibilities:
- Lead the development of UVM-based verification environments from scratch
- Architect and implement design verification infrastructure and execute the full verification cycle
- Collaborate with cross-functional teams to design and develop verification environments
- Develop and maintain verification scripts and tools using Python, TCL, Perl, and Shell
- Work with IP and integration verification teams to develop and execute verification plans
- Provide expertise in protocols such as AMBA, PCIe, DDR, USB, and Ethernet
- Stay up-to-date with industry trends and emerging technologies in design verification
Requirements:
- 7+ years of experience in design verification
- 8/10+ experience in StemVerilog/UVM methodology and/or C/C++ based verification
- 8/10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
- Experience with revision control systems such as Mercurial, Git, or SVN
What We Offer:
- Opportunity to work with a leading technology company
- Collaborative and dynamic work environment
- Competitive salary and benefits package
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