Digital Verification Engineer
2 days ago
**Overview of the Role:**
L&T Technology Services is seeking a highly skilled Digital Verification Engineer to join our team. As a key member of our verification group, you will be responsible for designing and implementing digital verification plans, creating verification test benches, and driving design verification to closure.
**Key Responsibilities:**
We are looking for a talented engineer with expertise in StemVerilog/UVM methodology and/or C/C++ based verification. Your primary responsibilities will include:
- Defining and implementing IP/SoC verification plans
- Buidling verification test benches for IP/sub-stem/SoC level verification
- Developing functional tests based on verification test plan
- Driving Design Verification to closure based on defined verification metrics
- Debugging, root-causing, and resolving functional failures in the design
**Qualifications and Skills:**
To be successful in this role, you will need:
- A Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience
- 8/10+ years of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
- 8/ 10+ years of experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
- Experience in developing UVM based verification environments from scratch
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
- Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
- Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
- Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience with revision control systems like Mercurial(Hg), Git or SVN
**Salary:** The estimated salary for this role is ₹1,200,000 - ₹1,800,000 per year, depending on location and experience.
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