Timing Expert

2 days ago

Thrissur, Kerala, India beBeeExpertise Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Title: Timing Expert

We are seeking an experienced Timing Expert to lead Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. The ideal candidate will have a strong background in STA tools, such as Synopsys PrimeTime and Cadence Tempus, and PNR tools, including Synopsys ICC2 and Cadence Innovus.

  • Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
  • Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
Qualifications and Skills:

The successful candidate will have a proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems. Proficiency in scripting languages, such as Tcl, Perl, and Python, is also essential. Additionally, experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems is preferred.

  • 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.

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