Principal Memory Compiler Specialist

6 days ago


Ahmedabad, Gujarat, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Overview

Our organization is seeking a highly skilled Senior Design Engineer to spearhead the development of innovative memory compilers and Fast Cache instances for next-generation Cores.

The ideal candidate will be responsible for achieving outstanding Power, Performance, and Area (PPA) through strategic design and verification processes.

We are looking for a talented engineer with a strong understanding of computer architecture and concepts.

  • Good grasp of SRAM architecture, Critical Path Modelling, Full Cut Analysis, and Monte Carlo Simulations.
  • Experience in design verification: Sense amplifier analysis, self-time analysis, and marginality analysis.
  • Understanding of high-speed/low-power CMOS circuit design, clocking scheme, Static and complex logic circuits.
  • Knowledge of physical implementation impact on circuit performance.
  • Strong understanding of high-performance and low-power circuit designs with exposure to FinFet technologies and bitcell stability analysis.

The selected candidate will lead a small team of designers and oversee the overall design process, ensuring timely completion and quality deliverables.

A minimum of 7 years of experience in SRAM/memory design margin, char, and quality checks is required. Experience with Cadence or Synopsys flows, as well as circuit simulation and optimization of standard cells, is an asset.

Excellent interpersonal skills and a proven track record of leading teams are essential for this role.


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