Leading RTL Principal Engineer Position

2 days ago

Thiruvananthapuram, Kerala, India beBeeDesign Full time ₹ 1,24,30,000 - ₹ 2,22,80,000

Job Title: Sr RTL Principal Design Engineer

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  • Design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.
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Responsibilities:

  • Work with the existing RTL, addition of new features into the RTL.
  • Ensure various customer configurations are clean as part of verification regressions.
  • Support customers, ensuring design is clean for LINT and CDC design guidelines.
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Requirements:

  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • 8-16 years of core RTL Design experience using Verilog is a must.
  • System Verilog experience and experience with UVM based environment usage/debugging is required.
  • PCIe/CXL/IDE experience is needed. Prior experience in implementation of complex protocols is a must.
  • Prior experience in IP development teams would be an added advantage.
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Bonus Skills:

  • Scripting knowledge is an advantage.

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