Career Opportunity: Senior Design Verification Engineer

Design Verification Engineer OpportunityWe are seeking a skilled Design Verification Engineer to join our dynamic team. This role offers an exciting chance to work on senior design verification projects, utilizing your expertise in UVM/SV.

About CompanyEspressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We...

About Company Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We...

Tips: UVM, Design Verification.Responsibilities- Develop UVM interface agents from scratch and integrate them into the testbench.- Develop sequences, testcases, functional coverage as per testplan.- Develop testplan by reading the specification in detail, present to the verification and design teams.- Understand the existing complex testbench and update it...

Tips: UVM, Design Verification.ResponsibilitiesDevelop UVM interface agents from scratch and integrate them into the testbench.Develop sequences, testcases, functional coverage as per testplan.Develop testplan by reading the specification in detail, present to the verification and design teams.Understand the existing complex testbench and update it to add...

Tips: UVM, Design Verification.Responsibilities- Senior DV engineer to develop UVM/SV-based testbench- Good knowledge of SV/UVM is a must.- Should have developed UVM/SV components like driver/monitor/scoreboard,- Individual contributor role- Exposure to protocols like AMBA, Serial protocols, PCIe, EthernetQualifications- 6 to 8 years of DV experience...

JD Design Verification• Understanding the business requirements and functional specifications of the IPs, subsystems and SOC• Creating Verification Environment Architecture document• Reviewing and Revising: working towards meeting agreed upon acceptance criteria• Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit,...

Design Verification Engineer OpportunityJob Summary:A seasoned verification specialist is required to drive the development and testing of complex SoC architectures. The ideal candidate will possess in-depth knowledge of SV and UVM methodologies, hands-on experience in sub-system and block-level verification, as well as a solid understanding of digital...

Job DescriptionThe OpportunityWe&aposre looking for the Wavemakers of tomorrow.Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today,...

7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodologyExperience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPISolid understanding of digital hardware design and Verilog HDL.Detailed understanding and experience of the current...