Senior Design Verification Engineer
4 weeks ago
Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We have created the popular ESP8266 and ESP32 series of chips, modules and development boards. By leveraging wireless computing, we provide green, versatile and cost-effective chipsets. We have always been committed to offering IoT solutions that are secure, robust and power-efficient. By open-sourcing our technology, we aim to enable developers to use Espressif's technology globally and build smart connected devices. In July 2019, Espressif made its Initial Public Offering on the Sci-Tech Innovation Board (STAR) of the Shanghai Stock Exchange (SSE).
Espressif's Technology Center in Pune (Baner), India focuses on Digital IP development, embedded software engineering and IoT solutions development for our growing customers.
About the Role
This is an opportunity to be a key player at a company with a great reputation in IoT semiconductor technology and growing business. We offer a great long-term opportunity in a true team environment. We are looking for exceptional engineers to help develop the next generation IoT/AI chips based on a revolutionary architecture. Role offers immense opportunity to learn and work on verification of complex designs and challenge your technical and innovation skills.
We need brains, ambition and passion to execute complete embedded software development lifecycle. The goal is to create scalable and optimized software systems. You will work closely with people who will encourage and inspire you to continuously improve.
Responsibilities
- Drive functional verification at IP level using UVM/SV test bench
- RISC-V CPU and Vector/AI accelerator IP verification
- Work closely with design team to define comprehensive feature test plans
- Perform functional and code coverage for logic verification sign-off
- Formal verification and Gate level sim methodology experience will be a plus
Qualifications
- M.Tech/ B.Tech in the field of VLSI/Electronics engineering.
- 4 to 8 years of experience.
- Proficiency in UVM/SV and C/C++ based functional verification
- Experience in UPF based low power design verification
- Automation skills in languages like PERL,PYTHON, Shell or Makefile.
- Team player, with good problem solving and communication skills.
About you
Interpersonal Skills
- Energetic, self-motivated
- Pro-active, oriented on execution
- Attentive to details and quality
- Team player
- Good communications and reporting skills
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