Senior Digital Fault Tolerance Architect

2 weeks ago

Guntur, Andhra Pradesh, India beBeeDigitalFaultTolerance Full time ₹ 2,50,00,000 - ₹ 3,00,00,000

Digital Fault Tolerance Engineer

At our organization, we're looking for a skilled DFT engineer to join our team. As a key member of our design cycle, you'll be responsible for developing and implementing Digital Fault Tolerance (DFT) architecture with a focus on Built-In Self-Test (MBIST) for advanced System-on-Chip (SoCs).

We're seeking an individual with hands-on experience in DFT who can work closely with our RTL, Physical Design, and Verification teams throughout the design cycle. If you have a strong background in ATPG, SCAN, and MBIST, along with excellent analytical and problem-solving skills, we'd love to hear from you.

Key Responsibilities:

  • Develop and implement DFT architecture with a focus on MBIST for SoCs.
  • Integrate MBIST Intellectual Properties (IPs), generate test insertion and verification infrastructure.
  • Work on DFT planning, insertion, simulation, and pattern generation.
  • Perform Automatic Test Pattern Generation (ATPG) and MBIST pattern generation and debug failures from silicon bring-up.
  • Collaborate with other teams throughout the design cycle.

Required Skills and Experience:

  • Bachelor's degree in Electronics or related field.
  • Minimum 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN, and MBIST.
  • Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
  • Solid understanding of scan insertion, ATPG, boundary scan, and Joint Test Action Group (JTAG).
  • Experience with memory test algorithms, repair analysis, and pattern generation.
  • Familiarity with scripting languages (TCL, Perl, Python) for automation.

What We Offer:

  • A dynamic work environment with opportunities for growth and development.
  • A competitive salary and benefits package.
  • The chance to work on cutting-edge projects and contribute to the success of our organization.

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