
Principal ASIC Engineer
2 days ago
We are seeking an experienced senior physical design engineer to join our team.
Key Responsibilities:
- Provide technical guidance, mentoring to physical design engineers.
- Interface with front-end ASIC teams to resolve issues.
- Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
- Timing closure on DDR2/DDR3/PCIE interfaces.
- Excellent communication skills.
Requirements:
- Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
- Expertise in scripting languages such as PERL, TCL.
- Strong Physical Verification skill set.
- Static Timing Analysis in Primetime or Primetime-SI.
- Good written and oral communication skills. Ability to clearly document plans.
- Ability to interface with different teams and prioritize work based on project needs.
We look for a candidate with 4-12 years of experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating and substrate-bias.
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