
Senior ASIC Designer
2 days ago
We are seeking a highly skilled ASIC Physical Design Engineer to join our team. The ideal candidate will have expertise in all aspects of physical design for full-chip/block implementations, including floorplanning, placement, budgeting, clock tree planning and analysis, scan re-ordering, clock tree synthesis, placement optimizations, routing, timing, and SI analysis/closure.
Key Responsibilities- Responsible for all aspects of physical design for full-chip/block implementations.
- Strong knowledge of EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, and internal tools.
- Work closely with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow.
- Experienced in design automation, with a strong understanding of timing constraints, SI prevention, and power reduction.
- Prior experience with Synopsys/Cadence/Mentor place and route tools is essential.
- Proficient in Unix/TCL/Perl programming languages.
- Good communication and presentation skills are required.
- 4+ years of experience in ASIC physical design.
- Experience with block implementation, extraction, timing, or full-chip designs.
- Strong hands-on TCL/Perl development skills.
- Strong communication skills.
- Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project.
- Track record of taping out complex chips on advanced process nodes.
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