
Senior ASIC/SoC Design Verification Lead
2 days ago
We are seeking a highly experienced Design Verification Manager to lead critical projects and teams within the Design Verification domain. The ideal candidate will have extensive experience in ASIC/SoC Design Verification and will be responsible for end-to-end technical leadership, project execution, and team management.
The successful candidate will lead Design Verification (IP/Sub-System/SoC level) projects ensuring on-time, high-quality delivery. They will define verification strategies, test plans, coverage goals, and closure metrics in alignment with industry standards.
The role involves providing technical guidance in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies. Collaboration with architects, designers, and DV engineers across global teams is essential to drive seamless execution.
The Design Verification Manager will manage multi-site DV teams, track progress, and mitigate risks through proactive planning. Status reporting, milestone reviews, and client interactions are also key responsibilities of this role.
Mentoring junior engineers and ensuring adherence to best practices in verification and project management is crucial. Additionally, driving continuous improvements in automation, regression efficiency, and verification productivity is expected.
Required Skills & Experience:- A minimum of 14 years of experience in Design Verification (IP / Subsystem / SoC level)
- Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification
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