
Advanced ASIC Design Specialist
2 days ago
We are seeking an experienced Senior Physical Design Engineer to join our team at Moschip. The ideal candidate will have a strong background in ASIC Physical Design and excellent communication skills.
Job Summary:
The successful candidate will be responsible for leading the design of complex ASICs, providing technical guidance and mentoring to junior engineers, and collaborating with cross-functional teams to resolve issues.
- Key Responsibilities:
- Top-Level Floor Planning: Perform top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI-aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs).
- Low Power Design: Implement low power design techniques such as Voltage Islands, Power Gating, and substrate-bias.
- Timing Closure: Achieve timing closure on DDR2/DDR3/PCIE interfaces.
- Technical Guidance: Provide technical guidance and mentoring to Physical Design Engineers.
- Interface with Front-End Teams: Interface with front-end ASIC teams to resolve issues.
- Strong Background in ASIC Physical Design: Have a strong background in ASIC Physical Design, including floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Experience with Cadence or Synopsys: Have extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
- Scripting Languages: Be proficient in scripting languages such as PERL, TCL.
- Physical Verification: Possess a strong Physical Verification skill set.
- Static Timing Analysis: Have expertise in static timing analysis in Primetime or Primetime-SI.
- Excellent Communication Skills: Demonstrate good written and oral communication skills, with the ability to clearly document plans.
- Team Player: Ability to interface with different teams and prioritize work based on project needs.
Qualifications:
Experience: 3 to 12 Years
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