Technical Lead for ASIC Physical Design
1 week ago
Role: Technical Lead
Experience: 7+ years
Location: Remote
- Master's degree in EE or ECE with extensive experience in ASIC Physical Design
- Expertise in EDA tools and flows, with a strong focus on Tempus and Primetime
- Thorough understanding of STA and timing closure methodologies
- Effective development of pre- and post-layout constraints for timing closure
- Exceptional communication skills with design teams and expertise in developing functional and DFT constraints
- Skilled in integrating IP-level constraints and creating multi-voltage and switching-aware corner definitions
- Strong understanding of RC and C models, including abstraction techniques like Hyperscale, ILM, and ETM
- Expertise in RC balancing and scaling analysis for full-chip clocks and critical data paths
- Proficient in automation tools like PERL, TCL, and EDA tool-specific scripting
- Ability to develop custom scripts for timing fixes and drive full-chip and custom DMSA
At Wafer Space - An ACL Digital Company, we're seeking an experienced Technical Lead to join our team. As a key member of our design team, you will be responsible for leading the development of our ASIC physical design capabilities.
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