Senior ASIC Physical Design Engineer

1 week ago


Bengaluru, Karnataka, India ACL Digital Full time
Technical Expertise:
  • Proficient in timing closure methodologies, including STA timing closure.
  • Develops pre- and post-layout constraints to ensure timing closure.
  • Collaborates with the design team to create functional and DFT constraints.
  • Integrates IP-level constraints.
  • Defines multi-voltage and switching-aware corner cases.
  • Understands RC/C model selection.
  • Experienced in abstraction techniques like Hyperscale, ILM, and ETM.
  • Analyzes full-chip clock and critical data path RC balancing and scaling.
  • Skilled in automation using PERL, TCL, and EDA tool-specific scripting.
  • Develops DMSA scripts for timing fixes.
Qualifications:
  • BE/BTECH/MTECH in EE/ECE with a strong background in ASIC Physical Design.
  • Extensive knowledge of EDA tools and flows, with a focus on Tempus and Primetime.
  • Minimum 7 years of experience in ASIC Physical Design.


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