Senior ASIC Physical Design Expert
3 weeks ago
As a key member of our design team, you will be responsible for leading the physical design of complex ASICs, with a focus on timing closure and STA. Your expertise in EDA tools and flows, particularly Tempus and Primetime, will be instrumental in driving our design success.
Key Responsibilities:
• Develop and implement detailed knowledge of EDA tools and flows, with a strong emphasis on Tempus and Primetime.
• Collaborate with the design team to develop functional and DFT constraints, ensuring seamless integration of IP-level constraints.
• Design and implement multi-voltage and switching-aware corner definitions, as well as RC/C model selection and understanding.
• Utilize abstraction expertise, such as Hyperscale, ILM, and ETM, to drive design efficiency and accuracy.
• Conduct RC balancing and scaling analysis of full chip clocks and critical data paths, ensuring optimal design performance.
• Develop and maintain custom scripts for timing fixes, leveraging PERL, TCL, and EDA tool-specific scripting expertise.
Requirements:
• BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design.
• 7+ years of experience in the field, with a strong track record of delivering complex ASIC designs on time and within budget.
• Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced design environment.
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