Optimized Memory Engineer

2 weeks ago


Hyderabad, Telangana, India beBeeMemory Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

As a memory layout engineer, you will work on developing compilers for memory layouts and designing high-performance cache instances. The goal is to achieve outstanding Performance, Power, and Area (PPA).

Key Responsibilities

• Design memory compilers and create optimized layouts.

• Collaborate with cross-functional teams to improve PPA.

• Develop in-depth knowledge of CMOS transistors, their behaviors, and logic design.

• Analyze power, performance, and area trade-offs in typical CMOS designs.

• Create high-quality design rule-driven layouts and review schematics with engineering to propose changes.

• Explore floor planning options and propose improvements.

• Develop expertise in SRAM/memory layouts creation and backend verifications including EMIR analysis.

Nice To Have Skills

• Basic scripting languages.

• Experience working on Cadence or Synopsys flows.

Requirements

• Bachelor's or Master's degree in Electronic Engineering or equivalent.

• 5+ years of experience in SRAM/memory layouts creation and backend verifications including EMIR analysis.

Must-Have Skills:

  • CMOS Transistor Knowledge
  • SRAM/Memory Layouts Creation
  • Cadence/Synopsys Flow Experience


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