Clocking Solutions Architect

6 days ago

Bengaluru, Karnataka, India beBeeBackendDesignLead Full time ₹ 15,00,000 - ₹ 28,00,000
Backend Design Lead Job Opportunity

This is a highly challenging and rewarding role that requires strong leadership skills, technical expertise, and excellent communication abilities.

We are seeking a seasoned Backend Design Lead to drive our design process and lead a team of engineers in delivering complex projects on time and with high quality. The successful candidate will be responsible for leading floor-planning, placement, routing, custom clock tree design, and optimization, as well as ensuring successful CAD flow from IP design to SoC/3DIC design.

The ideal candidate will have a deep understanding of clocking methodologies, experience in leading teams, and a proven track record in chip-level PNR and successful tapeouts of complex SoC designs. They should also be proficient in STA and methodologies for timing closure, have a good understanding of noise, cross-talk, Aging and OCV effects, among others, and be familiar with Verilog and system Verilog for design.

In addition to technical skills, the successful candidate will be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers.

Key Responsibilities:
  • Lead floor-planning, placement, routing, custom clock tree design, and optimization.
  • Ensure successful CAD flow from IP design to SoC/3DIC design.
  • Collaborate with design, Physical design, IT/infrastructure teams to ensure successful delivery of complex projects.
  • Develop and implement clocking solutions to meet project requirements.
  • Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure.
Requirements:
  • Bachelor or master degree in computer engineering/Electronics or Electrical Engineering.
  • 10+ years of hands-on experience in physical design and verification.
  • Proven track record in chip-level PNR and successful tapeouts of complex SoC designs.
  • Strong working knowledge of Programable clocking and Physical Design.
  • Expert knowledge of clocking methodologies and experience in leading teams.

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