Senior ASIC Timing Closure Specialist

24 hours ago

Kanpur, Uttar Pradesh, India beBeeTiming Full time ₹ 1,20,00,000 - ₹ 1,80,00,000
Job Description

We are seeking an experienced Senior ASIC STA Engineer to join our SOC digital design team. The successful candidate will be responsible for providing integrated solutions into a growth industry.

In this highly visible role, you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to customers quickly.

This is a fantastic opportunity for career development and growth.

Key Qualifications
  • Bachelor's/Master's/PhD degree in Electrical Engineering or related field with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
  • Knowledge of timing corners/modes and process variations.
  • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
Responsibilities
  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
  • Develop and maintain methodology and flows related to timing verification and closure.
  • Generation of block and full chip timing constraints.
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
  • Support digital chip integration work and flows
What We Offer
  • Opportunity to work on leading edge technologies
  • Career development and growth opportunities
  • Competitive compensation package
  • Medical benefits and more

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