Champion of Physical Design Excellence

4 days ago


Kanpur, Uttar Pradesh, India beBeePhysical Full time US$ 18,00,000 - US$ 24,00,000

Job Summary

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This position is for an expert in Physical Design who will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.

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The ideal candidate will have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. They should be able to work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow.

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The candidate must have prior experience with Synopsys/Cadence/Mentor place and route tools, as well as a strong background in design automation, understanding of Timing constraints, SI prevention, Power reduction.

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Key Responsibilities:

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  • Lead full-chip floorplanning, routing, or timing projects for large silicon initiatives.">
  • Collaborate with cross-functional teams to drive complex chip designs through advanced process nodes.">
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Requirements:

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  • 4+ years experience in ASIC physical design with expertise in block implementation, extraction, timing and/or full-chip designs.">
  • Strong hands-on TCL/Perl development skills.">
  • Proven track record of taping out complex chips on 16nm and 7nm process nodes.">
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Preferred Qualifications:

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  • Experience as a lead in full-chip floorplanning, routing, or timing for large silicon projects.">
  • Ability to communicate complex technical ideas effectively to both technical and non-technical stakeholders.">
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