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Senior Chip Designer
3 weeks ago
Job Overview
We are seeking an experienced SMTS Silicon Design Engineer to join our team. The successful candidate will be responsible for delivering the physical design of tiles and FullChip for next-generation processors.
Key Responsibilities- Handling RTL to GDS2 flow
- Floor-plan and Physical Implementation of Power-plan
- Synthesis, Placement, CTS, Routing, Extraction, Timing Closure, Tile level, Full chip Physical Verification, DRC, LVS, Crosstalk Analysis, EM IR
- Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
The ideal candidate will have 12+ years of professional experience in physical design, preferably with high-performance designs. Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications is also desirable.
Requirements- Bachelor's or Master's degree in Electronics or Electrical Engineering
- Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
- Excellent physical design and timing background
As an equal opportunity employer, we encourage applications from all qualified candidates and will accommodate applicants' needs throughout all stages of the recruitment and selection process.
