
Advanced DFT Architecture Engineer
3 days ago
Job Summary
We are seeking a DFT Architect to drive the development of test architectures and strategies for complex SoC/ASIC designs. This role requires a technical leader who can mentor junior engineers, collaborate with cross-functional teams, and ensure high-quality testability and manufacturability of silicon products.
Key Responsibilities:
- Develop and implement DFT strategies and architectures for multiple ASIC/SoC projects.
- Lead the implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation, MBIST, boundary scan, and IJTAG.
- Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
- Perform pattern generation, fault simulation, and debug test coverage gaps.
- Own DFT signoff, timing closure, and ATE pattern delivery.
- Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
Requirements:
- Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
- 7+ years of experience in DFT for complex ASIC or SoC designs.
- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
- Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
- Strong knowledge of RTL design, STA, and synthesis flows.
- Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
Benefits:
- Competitive salary and leadership exposure.
- Fast-track growth opportunities.
- Collaboration with top-tier engineers and global semiconductor leaders.
Why Work With Us?
- Drive innovation in the field of DFT architecture.
- Contribute to the development of next-gen SoCs and ASICs.
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