Timing Analysis Lead

3 days ago


Bengaluru, Karnataka, India Leadsoc Full time
About the Role

We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer to join our team at Leadsoc Technologies. As a Senior STA Engineer, you will play a critical role in ensuring the timing closure of complex System-on-Chip (SoC) designs.

You will be responsible for optimizing design performance, identifying and resolving timing issues, and collaborating with cross-functional teams to deliver high-quality products that meet customer expectations.

Key Responsibilities:
  • Perform advanced static timing analysis using industry-standard tools.
  • Analyze and optimize design performance to meet timing closure targets.
  • Identify and resolve timing violations through clock gating, power gating, and other optimization techniques.
  • Develop and implement STA methodologies to improve efficiency and accuracy.
Requirements:
  • 8+ years of experience in Static Timing Analysis (STA) of complex SoC designs.
  • Strong understanding of timing analysis fundamentals, including clock tree analysis, path analysis, and slack analysis.
  • Expertise in using industry-standard STA tools (Synopsys PrimeTime, Cadence Tempus).
  • Experience with multi-power domain designs and timing analysis techniques.

The estimated salary for this position is around $120,000 - $180,000 per year, depending on location and experience. This figure includes a base salary range, as well as additional compensation for bonuses and benefits. Leadsoc Technologies offers a comprehensive benefits package, including medical, dental, and vision insurance, 401(k) matching, and paid time off. Our company culture values collaboration, innovation, and professional growth, making us an attractive employer for top talent in the field.



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