High-Performance Timing Analysis Engineer

4 days ago

Bengaluru, Karnataka, India Jones RecruitZo Full time

Job Overview

We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer to join our team at Jones RecruitZo in Bengaluru or Hyderabad, India. This role offers a fantastic opportunity to work on cutting-edge IC designs and be part of a highly skilled engineering team focused on high-performance IC development.

About the Role

As a Senior STA Engineer, you will lead static timing analysis and closure efforts for complex digital designs at both the block level and SoC level. You will be responsible for ensuring that timing constraints are met across multiple operating conditions and corners.

Main Responsibilities

  • Timing Analysis: Perform static timing analysis (STA) at both the block and SoC levels using industry-standard tools such as Primetime and Tempus.
  • Constraint Development: Work with design and implementation teams to develop, define, and qualify timing constraints (SDC and constraint syntax) to ensure timing closure.
  • Industry Tools Expertise: Utilize industry-standard STA tools such as DMSA or Tweaker for analysis and signoff.
  • Timing Closure: Drive timing closure at both block and full-chip levels, including complex timing paths, multi-voltage designs, and advanced process nodes (7nm, 5nm, etc.).
  • MMMC & Timing Modes: Expertise in MMC (Multi-Mode Multi-Corner) analysis and handling different timing modes and corners effectively.
  • Collaboration: Work closely with physical design engineers to resolve timing-related issues during implementation.
  • ECOs: Generate and manage ECOs (Engineering Change Orders) for multi-voltage designs to meet timing requirements.
  • Timing Signoff: Own the timing signoff process at both block-level and full-chip-level, ensuring signoff criteria are met under various scenarios.

Requirements

To be successful in this role, you should have a Bachelor's or Master's degree in Electrical Engineering, VLSI, or related fields. Your experience should include 8+ years of experience in Static Timing Analysis (STA) for digital VLSI/IC designs, with expertise in both block-level and SoC-level timing analysis. Proficiency in industry-standard STA tools, strong understanding of SDC and timing constraint syntax, and proven experience in achieving timing closure for complex designs are essential.

Compensation

The estimated salary for this role is ₹20-30 Lakhs per annum depending on your location, skills, and experience. We offer a competitive compensation package, including a range of benefits designed to support your well-being and career growth.

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