Senior RTL Development Lead

4 days ago


Kanpur, Uttar Pradesh, India beBeeRtl Full time ₹ 30,00,000 - ₹ 50,00,000

Key Role:

A seasoned design engineer is required to spearhead the development of high-performance RTL designs using Verilog, with a focus on interface controller IP solutions.

Core Responsibilities:

  • Design and support the RTL of the PCIe/CXL/IDE/UALink IP solution
  • Collaborate with existing RTL, integrate new features, and ensure customer configurations are seamless
  • Provide expert support to customers, ensuring designs meet LINT and CDC guidelines

Essential Qualifications:

  • Bachelor's/Master's degree in Electrical / Electronics / VLSI Engineering
  • 8-16 years of core RTL Design experience using Verilog
  • Proficiency in System Verilog and UVM-based environments
  • Expertise in PCIe/CXL/IDE protocols and complex implementation


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