High-Speed Interconnect Architect Lead

15 hours ago

Kanpur, Uttar Pradesh, India beBeeInterconnect Full time ₹ 1,80,00,000 - ₹ 2,50,00,000
Job Description

A seasoned leader is required to spearhead the development of high-bandwidth, low-latency on-chip interconnects and chip-to-chip interconnects.

  • Design and architect different interconnect topologies as driven by bandwidth, latency, and RAS requirements.
  • Develop the features, present the proposed architecture in the High-level design discussion.
  • Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature.
  • Sign-off the Pre-silicon Design that meets all the functional, area, and timing goals.
  • Participate in silicon bring-up and validation of the hardware.
Required Skills and Qualifications

Master's Degree in Computer Science or related field.

At least 8 years of relevant experience in processor interconnect design delivery leadership.

  • Expertise in SMP coherency.
  • Experience in different on-chip interconnect topologies (e.g., mesh, crossbar).
  • Understanding of various snoop and data network protocols.
  • Understanding of latency & bandwidth requirements and effective means of implementation.
  • Working knowledge of queuing theory.
  • numa/nuca architecture.
  • Proficient in HDLs - VHDL / Verilog.
  • Experience in High-speed and Power-efficient logic design.
  • Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage.
  • Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage, and budgets, placement of blocks for achieving high-performance design.
  • Experience in leading uarch, RTL design teams for feature enhancements.

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