RISC-V CPU Cluster Lead Verification Engineer

5 days ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 10,42,158 - ₹ 24,71,359
Lead Verification Engineer for RISC-V CPU Clusters

As a Lead Verification Engineer for RISC-V CPU clusters, you will play a key role in architecting and developing world-class verification infrastructure to drive high-performance cluster and SoC development. Our team is seeking a passionate and hands-on professional with expertise in SystemVerilog, UVM, and C++ who can define and drive verification plans independently.

This is a great opportunity to collaborate with top-tier CPU designers and build from scratch innovative methodologies for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies.

Key Responsibilities:
  • Develop and execute verification strategies for multi-IP systems using SystemVerilog and UVM-based verification flows.
  • Design and implement stimulus planning, debug techniques, and coverage closure methods for complex hardware subsystems.
  • Work closely with cross-functional teams to ensure correct behavior at the cluster or SoC level.
Requirements:
  • A Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
  • 5-12 years of experience with SystemVerilog and UVM-based verification.
  • Proven ability to lead DV projects with integration and system feature validation responsibilities.
  • Familiarity with AXI/CHI protocols, System IPs flows, and integration flows for multi-IP verification environments.
What You Will Gain:
  • Expertise in scaling DV infrastructure for high-performance RISC-V clusters and SoCs.
  • Knowledge on verifying multi-agent interactions across CPUs, system IPs, and NoC or fabric components.
  • Best practices for cross-IP feature convergence, integration-level planning, and reuse across cluster/SOC programs.
  • Collaboration skills with global teams across RTL, DV, software, and validation for cohesive system-level bring-up.

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