RISC-V CPU Core Testbench Lead

2 weeks ago

Bengaluru, Karnataka, India Tenstorrent Full time

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

RISC-V CPU Core Testbench Lead

Responsibilities

  • Design, develop, and maintain highly configurable testbench environments for RISC-V cores and clusters using synthesizable SystemVerilog, UVM and C++.
  • Build key testbench components including harnesses, transactors, functional models, checkers and utilities such as preloaders, trickbox etc.
  • Contribute to the CVM (C++ Verification Methodology) - a UVM-inspired framework - by applying modern C++ features to simplify testbench development and improve maintainability.
  • Enable integration of UVM-based block-level environments into the broader testbench framework to support hybrid simulation workflows.
  • Ensure testbench portability across simulators (including open-source Verilator) and commercial emulation platforms.
  • Support architecture and microarchitecture bring-up for both core and cluster DV teams by enabling rapid validation of new features.
  • Develop debugging tools and automation to accelerate root-cause analysis for failures across simulation and emulation.
  • Collaborate closely with RTL, DV, and tooling teams to define reusable infrastructure and scalable test strategies.

Experience and Qualifications

  • Bachelor's or Master's degree in Electronics, Computer Engineering, or a related field, with 10+ years of relevant industry experience.
  • Strong proficiency in modern C++ and SystemVerilog, including familiarity with verification libraries or testbench infrastructure.
  • Hands-on experience with SystemVerilog UVM, including environment construction and integration into larger simulation contexts.
  • Experience working with or contributing to custom DV methodologies (e.g., UVM, custom C++-based frameworks).
  • Solid understanding of software engineering principles such as design patterns (e.g., publish-subscribe), multithreaded programming, and coroutines.
  • Working knowledge of CPU architectures (RISC-V, ARM, or x86) and microarchitectural design elements such as pipelines, caches, MMUs etc.
  • Strong debugging and analytical skills across layers of abstraction — from software and compiler traces to assembly programs and RTL waveforms.
  • Excellent communication and collaboration skills, with a track record of working effectively in fast-paced team environments.

Self-driven and adaptable, with a bias for automation, reuse, and scalable infrastructure.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

  • Core RISC-V Verification Specialist

    3 days ago

    Bengaluru, Karnataka, India beBeeRiscV Full time ₹ 8,00,000 - ₹ 12,00,000

    Core RISC-V Verification SpecialistThe ideal candidate will be responsible for leading the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications. This includes verifying that the cores and components comply with the RISC-V ISA and its extensions, as well as ensuring correct execution of instructions, exception...

  • RISC V Lead

    4 weeks ago

    Bengaluru, Karnataka, India UST Full time

    Hi, We have an opening for RISC V/ARM Verification engineer and Lead role with SV, UVM, Verilog. Should have hands on verification experience on processor based system, preferably RISC-V/ARM based verification experience. Understanding of RISC-V/ARM architecture Must have worked on multiple project on SV-UVM based methodology Scripting experience is an...

  • RISC-V Cluster Verification Expert

    1 day ago

    Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

    Job SummaryWe are seeking a Verification Engineer to design, develop and evolve verification infrastructure for high-performance RISC-V CPU clusters. This role involves architecting and defining verification plans for complex hardware subsystems.

  • CPU Verification Engineers

    2 days ago

    Bengaluru, Karnataka, India ACL Digital Full time

    CPU Verification EngineersExperience : 4+ yearsLocation : Bangalore & HyderabadWe are seeking a skilled and motivated CPU Verification Engineer to join our microprocessor verification team. In this role, you will contribute to the verification of Super scalar, high-performance, low-power CPU cores by developing scalable testbenches, driving complex test...

  • CPU Verification Engineers

    2 days ago

    Bengaluru, Karnataka, India ACL Digital Full time

    CPU Verification Engineers Experience : 4+ years Location : Bangalore & Hyderabad We are seeking a skilled and motivated CPU Verification Engineer to join our microprocessor verification team. In this role, you will contribute to the verification of Super scalar, high-performance, low-power CPU cores by developing scalable testbenches, driving complex...

  • CPU Verification Engineer

    1 day ago

    Bengaluru, Karnataka, India ACL Digital Full time

    CPU Verification EngineersExperience : 4+ yearsLocation : Bangalore & HyderabadWe are seeking a skilled and motivated CPU Verification Engineer to join our microprocessor verification team. In this role, you will contribute to the verification of Super scalar, high-performance, low-power CPU cores by developing scalable testbenches, driving complex test...

  • Design Verification

    4 days ago

    Bengaluru, Karnataka, India ACL Digital Full time

    RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...

  • Design Verification

    4 weeks ago

    Bengaluru, Karnataka, India ACL Digital Full time

    RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...

  • Design Verification

    2 weeks ago

    Bengaluru, Karnataka, India ACL Digital Full time

    RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions). Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...

  • Design Verification

    2 days ago

    Bengaluru, Karnataka, India ACL Digital Full time

    RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...