Senior Verification Expert for RISC-V Systems

6 days ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,80,00,000 - ₹ 2,40,00,000

RISC-V System IP Design Verification Engineer

We are seeking a highly skilled engineer to design, implement and evolve state-of-the-art verification infrastructure for next-generation System IPs.

This role is ideal for engineers who thrive on building from scratch, innovating verification methodologies and working closely with world-class CPU designers and architects.

Key Responsibilities:

  • Architect, develop and maintain UVM/SystemVerilog-based verification environments for complex RISC-V System IPs.
  • Define, execute and track comprehensive verification plans across IP, subsystem and SoC integration levels.
  • Design reusable verification components, checkers, monitors and coverage models that scale across multiple projects.
  • Drive stimulus planning, constrained-random test generation and advanced debug strategies to validate corner cases.
  • Collaborate with RTL designers, micro-architects and software/firmware teams to validate system-level use cases.

Requirements:

  • Bachelors/Masters degree in Computer Engineering/Computer Science.
  • 7-15 years of experience in System IP or SoC-level verification.
  • Demonstrated ability to lead IP-level and subsystem-level DV projects.

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