
RISC-V System IP Architect
1 day ago
We are seeking a skilled and innovative RISC-V system IP DV engineer to develop and evolve verification infrastructure for system IPs integrated into high-performance RISC-V CPU clusters.
This is a hybrid role based out of Bangalore, and we welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level.
Key Responsibilities:
- Creating robust verification environments using SystemVerilog and UVM
- Defining and driving verification plans independently
- Developing stimulus planning, checker development, debug techniques, and coverage closure for verifying complex hardware subsystems
- Designing plans to verify features spanning multiple IPs at IP, subsystem, and full-chip levels
Requirements:
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
- 7-15 years of strong experience with System Verilog and UVM-based verification
- Proven ability to drive IP-level and subsystem-level DV projects
- Familiarity with core MMU or SMMU/IOMMU, bus protocols like AXI
What You Will Learn:
- Owning a large scope with a small focused team
- Structuring and delivering a configurable IP to SoCs with seamless integration in mind
- Integrating IOMMU in a SoC, collaborating closely with RTL designers, architects, etc.
- Building reusable verification components, coverage models, and checkers that scale across multiple abstraction layers
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