
Risc-V design verification engineer
2 weeks ago
Hi All,
Key Skills : SV-UVM, RISC-V, Processor/Firmware based verification
Required experience : 6 to 8 yrs
Work location : Hyderabad/ Bangalore
Please share your resume to jayalakshmi.r2@ust.com
Regards,
Jaya
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Risc-V design verification engineer
4 weeks ago
Bengaluru, Karnataka, India UST Full timeHi All, Key Skills : SV-UVM, RISC-V, Processor/Firmware based verification Required experience : 6 to 8 yrs Work location : Hyderabad/ Bangalore Please share your resume to Regards, Jaya
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