Staff, Design Verification

2 days ago

Bengaluru, Karnataka, India Tenstorrent Full time

We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

  • You thrive in building robust verification environments using SystemVerilog, UVM and C++, and can define and drive verification plans independently.
  • You bring a system-level mindset, with experience integrating multiple IPs into clusters or SoCs and verifying their interactions.
  • You have a strong grasp of stimulus planning, debug techniques, and coverage closure for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies.
  • You're comfortable working on features that span multiple IPs — such as coherence, security — and ensuring their correct behavior at the cluster or SoC level.

What We Need

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
  • 5- 12 years of Strong experience with System Verilog and UVM-based verification.
  • Proven ability to drive subsystem or SoC-level DV projects with integration and system feature validation responsibilities.
  • Familiarity with AXI/CHI protocols, System IPs flows (like debug/trace, power management), and integration flows for multi-IP verification environments.

What You Will Learn

  • Techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs.
  • How to verify multi-agent interactions across CPUs, system IPs and NoC or fabric components.
  • Best practices for cross-IP feature convergence, integration-level planning, and reuse across cluster/SOC programs.
  • How to collaborate with global teams across RTL, DV, software, and validation for cohesive system-level bring-up.

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